In the art, the type of circuitry the present specification refers to as a "voltage boosting circuit" is variously referred to as "boosting circuit", "boosted voltage generating circuit", "Vpp generating circuit", or "bootstrap circuit". "MOS" is an acronym for "metal-oxide-semiconductor"; "PMOS" is an acronym for "p-channel, metal-oxide-semiconductor"; "NMOS" is an acronym for "n-channel metal-oxide-semiconductor"; "FET" is an acronym for "field effect transistor"; and "MOSFET" is an acronym for "metal-oxide-semiconductor field effect transistor". "CMOS" is an acronym for "complementary metal-oxide-semiconductor" and is used to describe an integrated-circuit technology using both p-channel and n-channel MOS field effect transistors. A logic inverter is referred to simply as an "inverter" in this specification and in the claims following this specification.
Generally considered, the information communication in a semiconductor memory device such as dynamic random access memory (DRAM) functions to move an effective potential. The potential in the DRAM constructed in CMOS transistor technology experiences a voltage drop of somewhat more than a threshold voltage of a MOSFET in the process of being transmitted by source-follower action. Such voltage drop causes information loss as well as acting as a considerable drawback in accurately performing data reading and writing operations. To solve such problem, a voltage boosting circuit is used to raise the level of the voltage. Prior-art voltage boosting circuits are disclosed in U.S. Pat. No. 5,367,489 issued 22 Nov. 1994 to Chah-Sok Park et alii, entitled "VOLTAGE PUMPING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICES" and assigned to Samsung Electronics Co., Ltd.; in a paper entitled "A 35 ns 64 Mb DRAM using On-chip Boosted Power Supply" on pp. 64-65 of 1992 Symposium on VLSI Circuits Digest of Technical Papers published in Korea; and in U.S. Pat. No. 4,704,706 issued to the Fujitsu company in Japan.
FIG. 1 is a circuit diagram illustrating construction of portions of a conventional voltage boosting circuit. In the figure, the voltage boosting circuit includes a transmission-gate transistor 18 which drives and transmits a boosted voltage Vpp from a boosting node 16 to a semiconductor memory device 19. In addition, the circuit has pumping capacitor 14 for pumping the Vpp, drivers 10 and 12 which supply the power supply to the pumping capacitor 14, and an oscillating circuit 9 which drives the cascaded drivers 10 and 12. A precharging circuit which initially precharges connecting nodes 8 and 16 to the power supply voltage Vcc level applied to the drivers 2, 4, 10 and 12 is also included in the circuitry, but is omitted from FIG. 1 because it does not relate to the problem to be solved by the invention.
In operation, upon power-up of a monolithic integrated circuit or the beginning of an active cycle, the oscillating circuit 9 starts to oscillate whenever the boosted voltage Vpp falls below a prescribed level. The connecting nodes 8 and 16 are initially precharged to the power supply voltage Vcc level applied to the drivers 2, 4, 10 and 12. The drivers 10 and 12 amplify the oscillating signal of the oscillating circuit 9 such that the output signal of the driver 12 is alternately switched between ground and Vcc potentials. When the output signal of the driver 12 switches to Vcc potential, this causes the pre-charged pumping capacitor 14 to raise the potential of the connecting node 16 to a level approximately equal twice the operating potential Vcc. Such a pumping operation will be performed in the drivers 2 and 4 and a pumping capacitor 6, in the same manner as discussed above, thereby raising a voltage of the connecting node 8 to a peak level approximately equal twice the operating potential Vcc. Thereafter, the peak voltage that the connecting node 8 is charged to is applied via the source-follower action of transmission-gate transistor 18 to the semiconductor memory device 19 as a boosted voltage Vpp.
In this manner, a boosted voltage Vpp level of 2 Vcc-Vth (wherein Vth represents the threshold voltage of the transistor 18) can be obtained. Thus, when the power supply voltage Vcc level is high (assuming that the Vcc level is over 3 volts), the boosted voltage Vpp level typically exceeds approximately Vcc+1.5 volts as a desired level, so that loss of the threshold voltage Vth caused by the transmission-gate transistor 18 not being fully conductive does not matter. However, if the Vcc level is below 3.0 volts, the voltage drop caused by the threshold voltage Vth in the Vpp level equal to 2 Vcc-Vth is relatively large, so there is difficulty in obtaining the full boosted voltage Vpp level when Vcc is low in level. Currently, the need to ensure punch-through gain places a lower limit on the value to which Vth can be reduced. The voltage boosting circuit as shown in FIG. 1 suffers from disadvantages in assuring its reliability, then, since appropriate action cannot be taken when the power supply voltage Vcc falls to low potential.
A voltage boosting circuit which assures high reliability despite low power supply voltage was sought by the inventor. A voltage boosting circuit which supplies a higher boosted voltage Vpp under low power supply voltage conditions was sought. A voltage boosting circuit which supplies a boosted voltage Vpp without occurrence of substantial voltage drop in the channel of a transmission-gate transistor was sought.